There are numerous types of semiconductor memory. Some memory is volatile and will lose its contents if power is removed. Some memory is non-volatile and will hold the information stored in the memory even after power has been removed. One type of non-volatile memory is flash memory. In a floating gate flash memory cell, a conductive floating gate, positioned between the control gate and the channel of a metal-oxide silicon field effect transistor (MOSFET), is used to store a charge and is thus referred to as a charge storage region. The threshold voltage of the MOSFET-based flash cell can be changed by changing the amount of charge stored in the charge storage region of the cell, and the threshold voltage can be used to indicate a value that is stored in the flash cell. One architecture for flash memories is a NAND flash architecture that utilizes negative-AND (NAND) logic gates. In a NAND flash architecture, two or more flash cells are coupled together, source to drain, into a string, with the individual cell control gates coupled to control lines, such as word lines. Select gates, which may be implemented with standard MOSFETs and are generally used during cell read and write operations, may be coupled to the NAND string at either end, to couple the NAND string to a source line at one end of the NAND string, and to a bit line at the other end of the NAND string.
Recently, NAND technology has gone vertical to form three-dimensional (3D) NAND structures. 3D NAND flash memory is suitable for the same types of applications that planar NAND (or 2D NAND) flash memory has been used, such as for solid-state memory. A stack of flash cells may include any number of flash cells with the source, channel, and drain arranged vertically so that as the cells are positioned, one on top of the other, they form a vertical NAND string. The vertical or 3D NAND string may be positioned on top of a select gate that may couple the string to a source line and may have another select gate positioned on top of the 3D NAND string to couple the string to a bit line. 3D NAND flash memory technology improves on planar NAND flash memory by stacking storage cells to increase capacity through higher density and lower cost per gigabyte, and 3D NAND also meets reliability, speed, and performance expectations for solid-state memory.
These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. Further still, some of the features in the drawings may include a patterned and/or shaded fill, which is primarily provided to assist in visually differentiating the different features. In short, the figures are provided merely to show example structures.